1. Field of the Invention
The present invention relates to amplifier circuits. More specifically, the present invention relates to switched capacitor CMOS amplifiers and operation thereof.
2. Description of Related Art
Many systems that manipulate and generate analog signals require amplification of those signals for presentation to other circuitry within the system. In Dynamic Random Access Memories (DRAM), as well as other semiconductor devices, amplifiers may be required in operational blocks such as sense amplifiers, input signal level sensors, phase locked loops, delay locked loops, general sensors, and various other analog circuits.
Regenerative receivers were first widely used in vacuum tube radio receivers. They provided a large signal gain, increased selectivity, an improved signal-to-noise ratio, and enabled the first widespread use of radio communication. This was accomplished with a minimal number of components by the use of positive feedback or “signal regeneration.” Positive feedback or regeneration allowed the same signal to be amplified many times by e same vacuum tube, resulting in a very high signal gain.
In feedback systems, whether negative or positive, the gain-bandwidth product generally remains constant. The positive feedback used in regenerative receivers served to increase the selectivity of the receiver since the bandwidth of the receiver decreased as the gain increased in order to preserve the gain-bandwidth product. A decrease in the bandwidth resulted in less noise interference and, when coupled with a higher gain, resulted in a much-improved signal-to-noise ratio and the new era of practical wireless communications was born.
In the modern era, positive feedback is employed in many digital Complementary Metal Oxide Semiconductor (CMOS) integrated circuits, such as sense amplifiers and level restore circuits. The positive feedback or regeneration results in a high effective transconductance (i.e., gain), with the ability to switch large capacitive loads in short time periods. However, in these digital circuits, the positive feedback gain is very large and the circuit is inherently unstable, The output from these positive feedback digital amplifiers is a large signal voltage generally intended to swing to a voltage level that may be interpreted as a one or a zero, rather than a small analog signal. Furthermore, positive feedback digital amplifiers generally produce a large non-linear output voltage, which is often limited by the power supply voltage (VDD). A cross-coupled positive feedback CMOS sense amplifier is an example of a widely used positive feedback digital amplifier, which enabled the common realization of many semiconductor memory types, such as Dynamic Random Access Memory (DRAM), and Static Random Access Memory (SRAM).
Analog CMOS amplifiers, on the other hand, amplify small analog signals and are generally configured to develop a stable gain on an output signal relative to an input signal without transitioning into an unstable or oscillating mode. Unfortunately, analog CMOS amplifiers are limited by the low gain inherent in MOS devices. The maximum gain of a single CMOS transistor, or the open circuit gain, may be as low as ten and typically is in the range of about twenty-five.
Switched capacitors coupled with a CMOS amplifier, in a conventional negative feedback configuration, can create a fixed gain determined by the ratio of capacitances for the overall switched capacitor CMOS amplifier. FIG. 1A illustrates a conventional switched capacitor amplifier 20 with negative feedback. The switched capacitor amplifier 20 shown in FIG. 1A includes a conventional operational amplifier 10 with a non-inverting input 12 connected to a ground voltage. A switched capacitor configuration couples an input signal 16 to an inverting input 14 of the operational amplifier 10. In a feedback path, another switched capacitor configuration couples the operational amplifier output 18 with the inverting input 14 of the operational amplifier 10.
This switched capacitor configuration is often termed a resettable gain circuit that functions as an amplifier during one phase of a clock cycle (ph1 in FIG. 1A) and is reset during a second phase of the clock cycle (ph2 in FIG. 1A). During the gain phase, ph1 is asserted and ph2 is negated. As a result, the n-channel transistors n11 and n15 are conducting while n-channel transistors n12, n13, and n14 are off. FIG. 1B illustrates an approximation of the amplifier circuit during the gain phase by removing the transistors that are off during the gain phase and showing the transistors that are on during the gain phase as a short circuit connection. The resulting circuit leaves a feed-in capacitor Cin coupled between the input signal 16 and the inverting input 14 of the operational amplifier 10 and a feedback capacitor Cc coupled between the operational amplifier output 18 and the inverting input 14 of the operational amplifier 10.
During the reset phase, ph2 is asserted and ph1 is negated. As a result, the n-channel transistors n12, n13, and n14 are conducting while transistors n11 and n15 are off. FIG. 1C illustrates an approximation of the amplifier in the reset phase by removing the transistors that are off during the reset phase and showing the transistors that are on during the reset phase as a short circuit connection. The resulting circuit leaves one side of the feed-in capacitor Cin and one side of the feedback capacitor Cc coupled to ground to reset the capacitors.
Unfortunately, as the gain of switched capacitor CMOS amplifiers increases, noise from the CMOS amplifier may increase even faster, resulting in a small signal-to-noise ratio. There is a need for CMOS amplifier circuits that can develop a higher stable gain relative to the signal-to-noise ratio.